Transistors are core building blocks for a majority of semiconductor devices. Some semiconductor devices, such as high performance processor devices, can include millions of transistors per device. Increasing transistor density by decreasing transistor size has traditionally been a high priority in the semiconductor industry.
However, with decreasing transistor size, printing of smaller gate geometries has been challenging due to the limitations of photolithography. The printed designs may appear distorted with irregularities, such as rounded edges, that optical proximity correction (OPC) is unable to compensate. Electrical properties of the transistors may be significantly distorted if such distortions are not corrected.
To ensure proper printability, a gate structure is formed and then “cut” using a cut mask to remove unwanted portions of the gate structure. This approach results in the most satisfactory printout of gate structures, and it is noteworthy that this approach applies for formation of different types of transistors, such as planar transistors and FinFETs.
As the gate structures in the transistors can be expected to have different widths, more than one the cut mask may be required to “cut” portions of the gate layer to ensure proper separation of the transistors. The need for multiple cut masks is likely to be costly.
As described above, there is a strong need to present a low cost fabrication method of forming gate structures having different widths using a gate cut process.